FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. Typical FPGAs include a plurality of programmable resources such as logic elements, memory blocks, and DSP blocks. When designing a multiplier on an FPGA, a traditional technique utilized the logic elements on the FPGA to build the multiplier. However, since a large number of logic elements were required to implement the multiplier, this technique resulted in producing a circuit having a large silicon size which was undesirable.
Other approaches used for designing a multiplier on an FPGA included using the DSP blocks on the FPGA. This technique produced a multiplier having a smaller silicon size which was an improvement over the traditional method of using logic elements. DSP blocks, however, have limited multiplier configuration flexibility. For example, a DSP block may support fixed configurations of only 9*9 bit, 18*18 bit, and 36*36 bit multiplication. When a multiplier has a configuration that exceeds a fixed configuration by even one bit, the next high resolution configuration would be required to implement that multiplier on the DSP block. Thus, this approach for multiplier design often resulted in unused multiplier resources on a DSP block. Survey results have indicated that when DSP blocks are used to implement multipliers on an FPGA, on average 75% of multiplier resources on the DSP blocks are unused. Since the number of DSP blocks on an FPGA is limited, this approach was not efficient from a resource utilization standpoint.
Thus, what is needed is an effective and efficient method for implementing multipliers on an FPGA.